1. Field of the Invention
The present invention relates to a method for fabricating an electronic component embedded substrate that includes an electronic component embedded within a multilayered circuit board.
2. Description of the Related Art
In recent years and continuing, the operating frequency of semiconductor elements mounted on semiconductor devices is rising, and in turn, measures are being demanded for stabilizing the source voltage supplied to the semiconductor element. In response to such a demand, an electronic component embedded substrate has been proposed that includes an electronic component (e.g., capacitor element) that is embedded within a semiconductor device substrate on which a semiconductor element is mounted.
Also, with the high densification of the semiconductor element, the pitch at which electrode pads are formed at the semiconductor element is becoming narrower. In turn, it is becoming difficult to form a wiring pattern with a sufficiently narrow pitch, corresponding to the pitch of electrode pads formed at the semiconductor element, on a conventional printed circuit board. Therefore, use of the conventional printed circuit board as a substrate for mounting a semiconductor element is becoming less suitable.
Accordingly, in recent years and continuing, a multilayered substrate that is referred to as a buildup printed circuit board is being used that includes a printed circuit board as a core layer and buildup layers and wiring layers laminated on each side of the core layer using the buildup method where the wiring layers are interconnected by vias. In the following descriptions, a layer formed using the buildup method and having wiring formed thereon is referred to as a buildup layer.
Conventionally, in the case of embedding an electronic component (e.g., capacitor element) in such type of multilayered circuit board, an electronic component is embedded within one single buildup layer (referred to as element embedded buildup layer) of the plural buildup layers included in the multilayered circuit board as is described in Japanese Laid-Open Patent Publication No. 2003-197809, for example.
Specifically, in a process according to the buildup method, after the element embedded buildup layer is formed, a cavity is formed thereon for accommodating a chip component (electronic component), and the electronic component is embedded in this cavity. Then, a buildup layer and a wiring layer are laminated on top of the element embedded buildup layer using the buildup method, and vias are formed at the layers. Also, terminals of the electronic component provided within the element embedded buildup layer and the wiring layer of the multilayered circuit board are arranged to be electrically connected by the vias.
As is described above, in the conventional electronic component embedded substrate, an electronic component is embedded in one buildup layer (element embedded buildup layer) of the laminated buildup layers. However, in an arrangement where an electronic component is provided within the element embedded buildup layer corresponding to one single buildup layer, the thickness of the electronic component is restricted by the film thickness of the element embedded buildup layer; that is, the electronic component has to be made thinner than the element embedded buildup layer.
Normally, buildup layers that are laminated using the buildup method have a film thickness of around 50 μm, and thereby, the thickness of the electronic component can be no more than 50 μm. However, it is quite difficult to fabricate an electronic component having a thickness of 50 μm or less, and the cost of such an electronic component is quite high. Also, there are obstacles with respect to improving the production yield for fabricating such an electronic component.